A phase splitter circuit is a widely used circuit that receives a clock signal and generates therefrom a pair of clock signals having a phase difference is 180° with respect to each other. For example, the phase splitter circuit has been used for controlling a switch of a pipeline and a double data rate signaling. An example of such a phase splitter circuit is disclosed in U.S. Pat. No. 4,782,253 entitled “HIGH SPEED MOS CIRCUITS”. FIG. 1 is a circuit diagram showing the phase splitter circuit disclosed in the '253 Patent.
Referring to FIG. 1, a phase splitter circuit 10 comprises first and second logic paths (first and second signal transfer paths) A and B. The first logic path A includes three inverters 21, 22, and 23 that are connected in cascade between an internal node NO and an input node N3 of a load (denoted by L). The second logic path B includes a pair of inverters 31 and 32 that are connected in cascade between the internal node NO and an input node N5 of another load (also denoted by L). The loads L consist of inverters 24 and 33, respectively.
Generally, each of the inverters of the first and second logic paths A and B is formed by a PMOS transistor and an NMOS transistor. Electrical current paths (source-drain paths) of the PMOS transistor and the NMOS transistor are connected in cascade between first and second power lines VDD and VSS. Gates of the PMOS and NMOS transistors are connected in common to receive an input signal. As known in the art, the output of the inverter is thus varied at a terminal located at a node in the series path between the PMOS and NMOS transistors. The internal node NO is typically connected to a clock pad (not shown) of a semiconductor integrated circuit (for example, a processor, memory or the like), i.e., to a clock pulse source thereof.
The above-described characteristic of the phase splitter circuit is directly linked with performance of a system having the phase splitter circuit. In addition, the characteristic of the phase splitter circuit may be evaluated depending on skew, a rise/fall time, low power, and a layout area. In this connection, the term “skew” refers to a difference between times A and B, where the time A is a time taken when the clock signal, rclk, is transferred to the output node N3 from the internal node NO, and the time B is a time taken when the clock signal, rclk, is transferred to the output node N5 from the internal node NO. Also, the rise/fall time determines whether transition waveforms of the clock signals clk and clkb, provided to loads 33 & 24 respectively, are similar. If the clock signals clk and clkb make similar waveforms, blocks using the clock signals clk and clkb as synchronous signals are guaranteed to exhibit a stable operating characteristic.
According to the above-mentioned '253 Patent, a delay matching method is used for improving the characteristic of the phase splitter circuit. The delay matching method is an application of the following principle. If the PMOS and NMOS transistors are designed such that delay elements are matched while matching delay times of the first and second logic paths A and B, the phase splitter circuit may obtain a stable characteristic with respect to process, voltage, and temperature variations (hereinafter referred to as “PVT variations”). Therefore, one advantage of such a delay matching method is that the phase splitter circuit is guaranteed to exhibit a robust characteristic, even though the PMOS and NMOS transistors are designed such that electrical characteristics thereof are contrary to each other.
According to the delay matching method, the sum Tup of pull-up delay times in the second logic path B is equal to the sum Tup of pull-up delay times in the first logic path A. Likewise, the sum Tdown of pull-down delay times in the second logic path B is equal to the sum Tdown of pull-down delay times in the first path A. As a result, the phase splitter circuit may be optimized with respect to the PVT variations. In this connection, a total delay time Td in the second logic path B is equal to Tup+Tdown. Similarly, a total delay time Td′ in the first logic path A is equal to Tup+Tdown. Under such matching conditions, the phase splitter circuit may be optimized with respect to the PVT variations, and a skew characteristic of the phase splitter circuit may be improved. However, the waveform mismatching between the clock signals clk and clkb cannot be adjusted by the phase splitter circuit as shown in FIG. 1 (Alternatively, the phase splitter circuit is not capable of adjusting the waveform matching between the clock signals clk and clkb). This will be described more specifically hereinbelow.
FIG. 2 shows the waveforms of the signals that are varied at each node of the phase splitter circuit shown in FIG. 1. In FIG. 2, time t1 is a pull-down time of an output signal of an inverter 31 (or a pull-down delay time of the inverter 31), and time t2 is a pull-up time of an output signal of an inverter 32 (or a pull-up delay time of the inverter 32). Time t3 is a pull-up time of the output signal of the inverter 31, and time t4 is a pull-down time of the output signal of the inverter 32. Time t5 is a pull-down time of an output signal of an inverter 21, and time t6 is a pull-up time of an output signal of an inverter 22. Time t7 is a pull-down time of an output signal clkb of an inverter 23. Also, time t8 is a pull-up time of the output signal of the inverter 21, and time t9 is a pull-down time of the output signal of the inverter 22. Time t10 is a pullup time of the output signal of the inverter 23.
In order to match pull-up times of the clk and clkb signal paths according to the delay matching method of the '253 Patent, the time t2 should be equal to the time t6, and the time t3 should be equal to the time (t8+t10). Likewise, in order to match pull-down times of the clk and clkb signal paths according to the delay matching method of the '253 Patent, the time t1 should be equal to the time (t5+t7), and the time t4 should be equal to the time t9. The above-mentioned conditions are optimum conditions for guaranteeing a stable skew characteristic and a stable duty characteristic with respect to the PVT variations.
In order to satisfy the equations t1=t5+t7 and t2=t6, the delay time t1 of the inverter 31 should equal the sum of the delay times 21 and 23, i.e., t5+t7, and the delay time t2 of the inverter 32 should equal the delay time t6 of the inverter 22. Under such conditions, the delay time t1 of the inverter 31 should be set to be much longer than each of the delay times t5 and t7 of the inverters 21 and 23 so that the delay time t1 of the inverter 31 may be equal to the sum of the delay times t5 and t7 of the inverters 21 and 23. In this respect, the inverter 31 should be designed such that an output loading capacitance of the inverter 31 is much larger than each output loading capacitance of the inverters 21 and 23. The output loading capacitance of the inverter 31 may be increased by an increase in a size of the inverter 32. However, as gate widths of transistors in the inverter 32 become excessively larger to increase the output loading capacitance of the inverter 31, a driving capacity of the inverter 32 also excessively increases. As a result, as shown in FIG. 2, the waveform (or transition slope) of the clock signal clk is sharply varied as compared with the waveform (or transition slope) of the clock signal clkb.
For reference, it is possible to use other techniques for increasing the output loading capacitance of the inverter 31. For example, gate lengths of the transistors in the inverter 32 may be increased. Alternatively, another capacitor may be added at the node N4. However, as a result of using such other techniques, the delay time t2 of the inverter 32 may be excessively increased. In this case, the delay matching of each element cannot be fulfilled.
In order to increase the delay time, there may be used an inverter circuit of which the pull-up and pull-down times are set by the PMOS and NMOS transistors. Such an inverter circuit is disclosed in U.S. Pat. No. 5,751,176 entitled “CLOCK GENERATOR FOR GENERATING COMLEMENTARY CLOCK SIGNALS WITH MINIMAL TIME DIFFERENCES”. However, the inverter circuit disclosed in U.S. Pat. No. 5,751,176 departs from the condition of the delay matching method of each element.
For this reason, as shown in FIG. 2, the rising/falling time tr_clk/tf_clk of the clock signal clk is shorter than the rising/falling time tr_clkb/tf_clkb of the clock signal clkb. As described above, since the output signals clk and clkb of the phase splitter circuit have different transition slopes, blocks or circuits using the output signals clk and clkb as the synchronous signals cannot exhibit stable operating characteristics. As a result, the system may suffer from deterioration of its performance.
FIGS. 3A and 3B are diagrams showing changes of the characteristics of the phase splitter circuit according to the PVT variations. FIG. 3C is a diagram showing variation of consumed currents of the phase splitter circuit according to the prior art.
In FIG. 3A, “ff”, “tt”, “ss”, “fs”, and “sf” are different process conditions. That is, “ff” is a process condition of a fast NMOS transistor and a fast PMOS transistor, and “tt” is a process condition of a typical NMOS transistor and a typical PMOS transistor. “ss” is a process condition of a slow NMOS transistor and a slow PMOS transistor, “fs” is a process condition of a fast NMOS transistor and a slow PMOS transistor, and “sf” is a process condition of the slow NMOS transistor and the fast PMOS transistor.
In this connection, the fast transistor, the slow transistor, and the typical transistor are divided according to a threshold voltage (or a saturation current: Id.sat) of each transistor.
Continuously, “Vdd_max” is about 2.626V; “Vdd_nom” is about 2.5V; and “Vdd_min” is about 2.25V. The skews between the clock signals clk and clkb when the clock signal rclk makes a low-to-high or high-to-low transition are denoted as “f_skew” and r_skew” respectively. As shown in FIG. 3A, when the PVT variations are varied as described above, the skew between the clock signals clk and clkb is controlled within ±13 ps (picosecond).
Referring to FIG. 3B, “tr/f_clk” is the rise/fall time of the clock signal clk, and “tr/f_clkb” is the rise/fall time of the clock signal clkb. As shown in FIG. 3B, there is a big gap between the rise/fall transition time of the clock signal clk and the rising/falling transition time of the clock signal clkb. Under typical test conditions, whereas the transition time (illustrated as solid lines) of clock signal clkb is about 170 ps, the transition time (also illustrated as solid lines) of the clock signal clk is only about 110 ps. For this reason, the clock signal clk generated through the second logic path has a much sharper waveform (or transition slope) as compared with that of the clock signal clkb generated through the first logic path. In other words, as shown in FIG. 3B, the transition time tr/f_clk of the clock signal clk is less than 50% of the transition time tr/f_clkb of the clock signal clkb with respect to all the PVT variations. As a result, sensitive analog circuits may suffer from severe deterioration of their characteristics.
In conclusion, according to the prior art, since the waveform matching characteristic between the output signals clk and clkb cannot be adjusted, it is impossible to optimize the phase splitter circuit. That is, the phase splitter circuit according to the prior art is not structurally capable of fulfilling both a delay matching characteristic of each element and balance of the transition time between the clock signals clk and clkb.